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PIC18F2XK20/4XK20

DS41297F-page 14

Advance Information

2009 Microchip Technology Inc.

FIGURE 3-2:

BULK ERASE TIMING DIAGRAM

3.1.2

LOW-VOLTAGE ICSP BULK ERASE

When using low-voltage ICSP, the part must be

supplied by the voltage specified in parameter D111 if a

Bulk Erase is to be executed. All other Bulk Erase

details as described above apply.

If it is determined that a program memory erase must

be performed at a supply voltage below the Bulk Erase

limit, refer to the erase methodology described in

Section 3.1.3 “ICSP Row Erase” and Section 3.2.1

“Modifying Code Memory”.

If it is determined that a data EEPROM erase must be

performed at a supply voltage below the Bulk Erase

limit, follow the methodology described in Section 3.3

“Data EEPROM Programming” and write ‘1’s to the

array.

3.1.3

ICSP ROW ERASE

Regardless of whether high or low-voltage ICSP is

used, it is possible to erase one row (64 bytes of data),

provided the block is not code or write-protected. Rows

are located at static boundaries beginning at program

memory address 000000h, extending to the internal

program memory limit (see Section 2.3 “Memory

Maps”).

The Row Erase duration is self-timed. After the WR bit

in EECON1 is set, two NOPs are issued. Erase starts

upon the 4th PGC of the second NOP. It ends when the

WR bit is cleared by hardware.

The code sequence to Row Erase a PIC18F2XK20/

4XK20 device is shown in Table 3-3. The flowchart

shown in Figure 3-3 depicts the logic necessary to com-

pletely erase a PIC18F2XK20/4XK20 device. The timing

diagram for Row Erase is identical to the data EEPROM

write timing shown in Figure 3-7.

215 16

PGC

P5A

PGD

PGD = Input

P11

P10

Erase Time

15 16

P5A

000

4-bit Command

16-bit

Data Payload

16-bit

Data Payload

16-bit

Data Payload

Note:

The TBLPTR register can point at any byte

within the row intended for erase.

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